CPU Circuit Design Engineer

Intel Corporation•Austin, TX

1d•Hybrid

About The Position

Join Intel as a CPU Circuit Design Engineer and contribute to designing and advancing cutting-edge digital circuits that form the backbone of Intel's high-performance CPUs. This role is integral to achieving power, performance, and area optimization while ensuring robust functionality and electrical capabilities. As part of a cross-functional team, you will drive innovation in a collaborative, fast-paced environment, helping shape the future of CPU design and technology. Your work will have a direct impact on Intel's success as a global leader in technology.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with 4+ years of experience; or Master's degree with 3+ years of experience; or a PhD.
Proficiency in CMOS circuit design, digital logic optimizations, and circuit trade-offs for power, performance, and area.
Expertise in Very Large Scale Integration (VLSI) circuits and design methodologies.

Nice To Haves

Experience in low-power implementation techniques and memory design.
Familiarity with circuit and layout trade-offs for optimized design.
Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis.
Strong analytical and problem-solving skills, with the ability to prioritize tasks and work in dynamic environments.

Responsibilities

Design, develop, and build custom digital circuits, including memory and caches, with a focus on power, performance, area, timing, and yield optimization.
Create floorplans, perform circuit design, schematic entry, and simulation for CPU blocks, and verify functionality for optimal design.
Collaborate with architecture and layout teams to ensure robust circuit designs with high electrical capabilities.
Develop and implement methodologies to streamline design flows and optimize performance, power, and area trade-offs.
Conduct signal integrity analysis to minimize noise glitches and reduce leakage of CPU circuits.
Create block-level DFT models, develop memory test tools, and manage characterization of individual memory instances and memory compilers.
Define and execute post-silicon speed-path analysis, bin-split, and power and performance projection tasks.
Report design progress, collect feedback, and address performance issues while adhering to project schedules.