Associate Engineer, Physical Design Engineering

Analog Devices • San Jose, CA

2d

About The Position

Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare. ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future. About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). About the Role We are seeking a New College Graduate Physical Design Engineer to join our high-impact Silicon Engineering team. You’ll work on next-generation IP (eFPGA) designs for AI, data center, and connectivity applications — collaborating closely with front-end and verification teams to deliver industry-leading silicon. As part of our Physical Design organization, you will be hands-on with advanced-node implementation flows (16nm,5nm, 4nm, and beyond), gaining exposure to the full ASIC backend cycle from RTL to GDSII.

Requirements

• M.S. or B.S. in Electrical Engineering, Computer Engineering, or related field (M.S. preferred).
• Strong academic foundation in VLSI design, CMOS fundamentals, digital logic, and timing analysis.
• Understanding of the ASIC design flow — from RTL through P&R and signoff.
• Familiarity with EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Ansys RedHawk, etc.).
• Working knowledge of Tcl, Python, or Shell scripting.
• Excellent analytical and debugging skills, with a strong attention to detail.
• Effective communicator and team player with a desire to learn and innovate.

Nice To Haves

• Internship or project experience in Physical Design or ASIC implementation.
• Exposure to timing ECO, low-power design (UPF), and DFT integration.
• Understanding of power-performance-area (PPA) tradeoffs.
• Familiarity with clocking and power intent (multi-voltage/multi-domain) concepts.

Responsibilities

• Contribute to block- and top-level implementation, including floor planning, placement, CTS, routing, and optimization.
• Perform timing closure, power optimization, and physical verification across multiple corners and scenarios.
• Collaborate with RTL and synthesis teams to resolve timing and congestion bottlenecks.
• Support signoff analysis including STA, IR-drop, and EM.
• Develop scripts and automation in Python, Tcl, or Shell to enhance flow efficiency.
• Participate in ECO (Engineering Change Order) implementation and final tape-out activities.
• Engage in regular cross-functional reviews with architecture, low-power, and packaging teams.
• Document and present learnings as part of continuous improvement within the Physical Design flow.

Benefits

• Hands-on training in advanced-node physical design flows (16nm/5nm/4nm).
• Opportunity to contribute to production-quality silicon tape-outs early in your career.
• Competitive compensation, comprehensive benefits, and flexible work options.
• A culture of innovation, collaboration, and continuous learning.
• medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level