Physical Design Engineer

Broadcom•San Jose, CA

About The Position

Broadcom is looking for a senior level RTL synthesis engineer. Qualifications include: MS in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design. Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Deep knowledge about industry standards in Physical aware synthesis. Experience in developing and implementing DFT flow. Experience with CDC, RDC, static timing analysis methodologies and relevant tools. Expert with developing automation scripts and design flow. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failure. Perform RTL Lint and work with the Designers to create waivers. Expert in generating Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development. Highly Desired Qualifications: Understanding of Cadence tools - Genus, Joules, Conformal. Understanding of Power analysis tools - Redhawk. Deep understanding of Signal Integrity and Power Integrity for High Speed designs. Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Excellent time and task management, and interpersonal skills.

Requirements

MS in Electrical Engineering or Computer Engineering
10+ years of experience in Physical design
Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist for Timing, Area, Power
Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
Deep knowledge about industry standards in Physical aware synthesis
Experience in developing and implementing DFT flow
Experience with CDC, RDC, static timing analysis methodologies and relevant tools
Expert with developing automation scripts and design flow
Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failure
Perform RTL Lint and work with the Designers to create waivers
Expert in generating Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
Analyze the inter-block timing and come up with IO budgets for the various partition blocks
Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development

Nice To Haves

Understanding of Cadence tools - Genus, Joules, Conformal
Understanding of Power analysis tools - Redhawk
Deep understanding of Signal Integrity and Power Integrity for High Speed designs
Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results
Excellent time and task management, and interpersonal skills

Responsibilities

Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist for Timing, Area, Power
Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
Developing and implementing DFT flow
Developing automation scripts and design flow
Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failure
Perform RTL Lint and work with the Designers to create waivers
Generating Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
Analyze the inter-block timing and come up with IO budgets for the various partition blocks