ASICS Engineer, Principal/Manager
About The Position
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work! The candidate will work in a team-oriented, professional engineering environment to perform a variety of signal and power integrity tasks and collaborate with package and IC designers to optimize the overall package design, including: Electrical model extraction and signal and power integrity simulations will constitute the majority of the tasks. Interfacing with a variety of board, package, and IC designers. Working effectively across organizational boundaries is essential, as is effective documentation and presentation of results. This candidate’s main functional area is high-speed SerDes/memory interface electrical model extraction and system-level simulation, such as PCIe, USB, UFS, and DDR.
Requirements
- 10+ years of experience with 5+ years in DDR/SerDes in Package/PCB/System Design related to compute/server standards.
- Experience in electromagnetics and a solid background in transmission line theory and crosstalk.
- Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity, and SPICE transient simulation (ADS, Hspice), including use of IBIS and IBIS AMI models.
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience.
- Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 7+ years of System/Package Design/Technology Engineering or related work experience.
- PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ year of System/Package Design/Technology Engineering or related work experience.
Nice To Haves
- Experience in SerDes design specifications such as PCIe, USB, UFS, and MIPI.
- Experience in DDR design specifications such as DDR and LPDDR
- Experience in Matlab to automate existing simulation flow.
- Experience in programming languages (C/C++) or scripting languages (Perl/Python) is a plus.
- Master’s or Ph.D. degree with 10+ years of industry experience.
Responsibilities
- Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include a variety of serial and memory interfaces.
- Apply established methodologies to analyze IO power distribution in product development and reference systems.
- Perform package extraction for time domain and frequency domain analysis and provide design guidelines for the package design.
- Create clear and complete documentation of results.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Number of Employees
5,001-10,000 employees
