ASIC Timing and Methodology Engineer
About The Position
As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies). You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation. Responsible for Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus. You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in class timing ECO tools . Work on timing sign off specification for different projects and support timing sign off for complex SOC’s. Hands on contribution for STA timing sign off. A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus. You should have good execution knowledge. Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production. You should have good programming skills Python, Perl, TCL, Unix shell , C/C++. ML modeling experience is a plus
Requirements
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Good understanding of RTL to GDS digital flow
- Good execution knowledge.
- Good programming skills Python, Perl, TCL, Unix shell , C/C++.
Nice To Haves
- Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus
- ML modeling experience
Responsibilities
- Timing analysis
- Design innovative SOC products
- Timing closure
- Flow scripts/tools development and validation
- Spice simulations for PVT corners validation and STA vs spice correlation
- Timing package validation across advanced process technologies using PT/PT-SI and Tempus
- Drive STA methodology for Qualcomm using PT-SI, Tempus and best in class timing ECO tools
- Support timing sign off for complex SOC’s
- STA timing sign off
- Understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required
- Improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
