Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture of next‑generation L1 accelerators from blank page to silicon. If you thrive on translating complex DSP/FEC algorithms into high-performance SystemVerilog, making tough power/area/throughput trade-offs, and delivering end-to-end IP in a lean, high-impact team—this is the role where your work will be seen and felt across world-class telecom products Step into a role where you’re not just another engineer—you’re a core architect of breakthrough telecom hardware. At Ericsson’s Accelerator IP team, we’re designing custom microarchitecture accelerators for EMCA L1 processing that push the boundaries of performance and innovation. Here, you’ll work in a small, elite team where your ideas shape products used worldwide—and your contributions have a direct line to impact. Forget being siloed: you’ll own major blocks end-to-end, from the first spark of concept to the final hand-off. If you thrive on turning complex algorithms into cutting-edge hardware and enjoy the adrenaline of building something from the ground up, this is your arena.
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Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
Number of Employees
5,001-10,000 employees