ASIC Design Verification Engineer
About The Position
Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency. We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers. This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.
Requirements
- Self motivated personality with a strong presence to do things right.
- Need to have a strong sense of teamwork and ability to work well with other.
- Constrained random verification methodologies with experience driving completion via coverage closure.
- Preferable to have skills with SV and UVM, well versed in OOP
- System Verilog (TB structures - Class, SVA, etc.)
- UVM
- VCS
- Incisive
- Scripting skills a + (Python, Perl, ...)
- Bachelors and 8+ years of related experience or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
