ASIC Design Verification Engineer (All Levels)

Marvell Technology

1d•Onsite

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Design Verification Engineer with Marvell, you’ll be a member of the Custom Compute and Solutions group. This group works on state-of-the-art datacenter and AI SoCs, and you will be responsible for verifying the circuitry. As a member of the R&D team, you will have the opportunity to work on world-class hardware for some of the biggest names in industry. We have multiple openings available, across levels. This position will be in San Diego, on-site. Compensation will be adjusted based on level. What You Can Expect In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete. Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues. Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs. Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment. Unit and regression testing of software tools.

Requirements

BS Computer Engineering, Electrical Engineering, or Computer Science with 4-10+ years of verification experience or MS/PhD with 2-10+ years experience).
Experience with SystemVerilog, UVM.
Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
Experience with scripting language such as Python or Perl and EDA Verification tools.
Experience with Object-Oriented Design and implementation.
Good understanding of Linux O.S.
Good programming skills desired, especially C++ and ARM assembly.
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
Requires the ability to accept and work with differing opinions.
Cannot be a close-minded developer.
Must be able to learn on the fly and work in a fast-paced environment.

Nice To Haves

Understanding of networking protocols, a plus.

Responsibilities

Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.
Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
Developing tests and tuning the environment to achieve coverage goals.
Debugging failures and working with designers to resolve issues.
Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
Unit and regression testing of software tools.