ASIC Design Verification Engineer

Cisco • San Jose, CA

12d

About The Position

Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact
As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.

Requirements

• Bachelors degree + 5 years of ASIC experience, or Masters degree+ 3 years of ASIC experience, or PhD + 0 years of related experience.
• Experience in System Verilog and UVM methodology
• Hands-on experience building reusable and scalable test benches from scratch
• Proficient in interactive and waveform debug skills

Nice To Haves

• Experience with scripting using Perl, TCL and/or Python.
• Effective written and verbal communication skills
• Collaborative and team-focused with the commitment to learn and grow
• Understanding of networking and packet forwarding architectures highly desirable
• Knowledge of formal verification tools (e.g., Jasper or VC Formal)
• Experience with RTL Design desirable
• Familiarity with ASIC/SoC design flow

Responsibilities

• Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
• Build DV environments from scratch for block and cluster levels
• Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus
• Ensure comprehensive verification coverage through code and functional coverage implementation and review
• Qualify RTL design by running Gate Level Simulations on netlists
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration
• Support design testing in emulation environments

Benefits

• U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
• Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level