ASIC Design Engineer

Meta • Sunnyvale, CA

54d

About The Position

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

Requirements

• Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, or a related field and 3 years of experience in the job-offered or in a related occupation
• Requires 3 years of experience in the following: Verilog or System Verilog
• Micro-architecture and RTL development for complex control and data path IPs
• Experience in SoC Micro-architecture, Design and Integration
• Experience in CPU, NOC, Memory, Peripheral Subsystems or Video Codec designs
• Synthesis, Timing Closure or Formal Verification Methodology
• TCL, Python, Perl, or Shell-scripting
• Working with complex control and data path IPs

Responsibilities

• Responsible for micro-architecture development.
• Perform RTL development using Verilog, System Verilog and/or HLS.
• Responsible for Lint, CDC, Synthesis, & Power Optimization.
• Collaborate with verification and emulation teams in test planning, development, and debugging.
• Collaborate with implementation team to close the design on timing and power.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level