ASIC Design Engineer Staff

Hewlett Packard Enterprise-posted 6 days ago

Full-time • Mid Level

Hybrid • Sunnyvale, CA

5,001-10,000 employees

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HPE networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting-edge networking chips used to build world-class routers and switches. Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips. As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex blocks where you can challenge yourself and grow. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.

Architect complex modules and subsystems used in high performance networking chips.
Write detailed functional as well as the micro-architecture specification for your module that meets power/area/performance targets.
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs.
Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
Work with Physical design team for optimal floorplan and timing closure.
Identify and fix timing in RTL to meet the frequency target.
Work with the Verification team to make sure your block is fully validated.
Provide guidance and mentoring to new college-grad engineers and interns.

Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 10+ years of relevant experience.
Strong analytical/ problem solving skills.
Demonstrated skills in leading and implementing high performance modules from specification to final netlist.
Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
Strong coding skills in Verilog/System Verilog through previous work experience are necessary.
Knowledge of synthesis/lint and other state-of-the-art EDA tools used in typical ASIC development process is highly desired.
Excellent written and verbal communications skills is necessary.
Knowledge of Perl/Python is strongly desired.

Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

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