Analog IC Design Intern

d-Matrix • Santa Clara, CA

1d • Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.
We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
Location:
Hybrid, working onsite at our Santa Clara office 3 days per week.
12 Week Program: June 1st - August 21st or June 22nd - September 11th
The role: Analog IC Design Intern
As an Analog IC Design Intern, you will assist in the circuit design, and performance verification of high-speed analog front-ends. This role focuses on the physical layer (PHY) components that enable low-power, high-bandwidth communication between chips in a multi-die package.

Requirements

• Education: Currently enrolled in a Graduate program (MS or PhD) in Electrical Engineering with a focus on Analog/Mixed-Signal IC Design.
• Core Knowledge:
• Strong foundation in CMOS/FinFET device physics and circuit fundamentals (Op-amps, PLLs, or SerDes).
• Understanding of high-speed transmission line theory and signal integrity.
• Technical Skills:
• Proficiency with Cadence Virtuoso (Schematic/Layout) and circuit simulators.
• Familiarity with scripting for data analysis (e.g., Python or MATLAB).

Nice To Haves

• Experience with mixed-signal verification flows and behavioral modeling in Verilog-A.
• Prior exposure to transceiver architectures (RX/TX), ADCs or clocking circuits like PLLs/DLLs.
• Familiarity with 2.5D/3D packaging constraints and their impact on analog circuit performance.

Responsibilities

• Circuit Design & Schematic Entry: Assist in designing critical analog blocks for D2D links, such as high-speed drivers, receivers, clock distribution networks, and voltage regulators.
• Simulation & Analysis: Perform detailed transient, noise, and Monte Carlo simulations using industry-standard tools like Cadence Virtuoso and SPICE.
• Performance Verification: Validate key performance metrics including Signal Integrity (SI), power consumption, and jitter to ensure compliance with standards like UCIe or proprietary chiplet protocols.
• Behavioral Modeling: Develop high-level behavioral models (e.g., in Verilog-A or MATLAB) to speed up top-level system simulations.
• Layout Support: Work with layout engineers to oversee critical physical design aspects, ensuring proper shielding and matching to minimize parasitic effects.
• Documentation & Review: Document design methodologies and present simulation results during internal technical reviews.

What This Job Offers

• Career Level: Intern