Analog Circuit Design Engineer

AlteraSan Jose, CA
7d

About The Position

About Altera For decades, Altera has been a leader in programmable logic solutions, enabling customers across aerospace, automotive, data center, communications, and industrial markets to deliver innovative, high-performance systems. As part of our continued growth, we are expanding our mixed-signal and analog design capabilities to support next-generation FPGA and SoC platforms. About the Role As an Analog/Mixed Signal Design Engineer you will be part of a team designing various analog/mixed-signal circuit designs on Intel FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP etc. on advanced processes nodes and have an opportunity to work on a diverse set of blocks and tasks in all phases of the design. The ideal candidate will be an independent self-starter who can own/design an analog IP and deliver all aspects of the design and collateral, a motivated team-player who is able to work with cross-functional and cross-geo teams to understand, articulate and solve problems, and an excellent communicator who is able to represent the team in meetings and forums and a leader, willing to provide mentorship to junior analog design engineers.

Requirements

  • BSEE/MSEE/PhD in Electrical Engineering or equivalent field with a minimum of 10 years of experience in analog/mixed signal, high speed, or high voltage IO designs and the following:
  • Direct design experience with analog and mixed signal circuits like amplifiers, comparators, regulators, IO, PLL etc
  • Experience in analog/mixed signal circuit design and layout flow and running post-layout simulations
  • Experience in analog design trade-offs and design for process variation and reliability in modern CMOS technologies
  • Experience in circuit design tools like Virtuoso, Spice, StarRC, Totem etc
  • Experience of Verilog, static timing analysis, UPF and related aspects of mixed signal design

Responsibilities

  • Technical path-finding, innovation, micro-architecture and design of analog/mixed-signal circuits including regulators and bandgaps to meet architectural specifications in advanced process nodes.
  • Contribute to architectural trade-off studies and design methodology improvements.
  • Design, develop and deliver circuit building block schematic, perform pre layout and post layout design optimization to meet design specification across PVT, process variation sensitivity analysis, aging, EOS, RV checks for design reliability.
  • Work with custom layout team to define plan (floorplan, routing, matching, metal grid etc) to meet circuit performance
  • Collateral generation like circuit Integration spec, BMOD, timing model, power model, ICCT, IBIS, alpha numbers.
  • Own specifications and design verification plans covering functionality, performance and reliability meeting high volume productization requirement.
  • Collaborate with logic designer, logic verification designer, structural physical design engineers, integration engineers, signal integrity and power deliver engineer to define clear collateral handoff requirements to ensure efficient IP integration.
  • Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification.
  • Conduct design reviews; actively contribute to design reviews
  • Represent the team on related IP in cross-functional meetings and co-ordination of deliverables
  • Work with external IP vendors as point of contact for analog designs
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service