AMS Verification Engineer

Analog Devices•Wilmington, MA

About The Position

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Verification Engineer - Full Time Position FY26 Recruiting Job level: P3 Job title: AMS Verification Engineer The ATE Group is currently seeking a motivated AMS Verification Engineer for the IC development of new products. Products in this strategy are comprised of integrated high speed and precision signal chains targeted towards Automated Test Equipment (ATE) applications. Product designs utilize both advanced internal BiCMOS SiGe processes as well as standard 0.18um/16nm CMOS processes. These designs are then combined on a laminate package to provide a custom SIP (System In a Package) solution otherwise known as a chiplet. The candidate’s responsibilities will include system level verification of the products including simulation of digital and mixed signal circuits including high speed drivers and receivers, DACs, SPI/JTAG/SerDes interfaces, calibration routines and digital controls. This is a multi-die verification effort utilizing both Verilog and spice simulators. A Verification plan will be created at the product start determining the verification methods to be utilized and the block model plans. Duties also include working with evaluation engineers to compare and contrast simulation and lab results. The ideal candidate is a self-motivated individual and fast learner with strong technical, analytical and communication skills. The candidate will have the opportunity to learn system level design experience, work with newly developed internal BiCMOS processes and collaborate closely with an experienced development team.

Requirements

Minimum requirement of BSEE, MSEE and 3+ years experience preferred
Knowledge of System Verilog, UVM and OOP
Knowledge of Verilog and Spice simulators
Knowledge of Analog circuits and CAD tools (Cadence Virtuoso).
Knowledge of a scripting language such as Python, TCL, Perl, Bash.
Ability to problem solve at the circuit and system level
Good presentation and writing/communication skills.
Ability to collaborate in a team environment and across organizations

Responsibilities

Develop test bench environments and directed functional, random, and constrained random tests.
Implement coverage driven verification methodologies.
Create functional coverage metrics.
Ensure these environments allow verification, design, product, and test engineers to efficiently develop functional test cases.
Define and develop block level modeling and verification strategies based on design requirements and architecture
Specify, and perform as necessary, block and chip level RTL, gate, and mixed signal co-simulation regressions.
Track progress against verification plan
Work with designers and product/apps engineers to achieve functional coverage goals and to debug the design and environment
Work closely with evaluation engineers when silicon arrives to compare and contrast simulation results
Participate in project meetings