Advanced Packaging Technology Pathfinding and Development Engineer

Marvell Technology•Austin, TX

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging R&D team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies. What You Can Expect Develop packaging technology roadmap for AI XPU, XPU-attach and Switch Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance. Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization. Explore technology feasibility and create proof-of-concept samples and productize technologies. Define package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope. Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability. Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis. Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements. Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost. Drive package qualification and reliability validation to volume readiness. What We're Looking For Experience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management. Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries. Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies. Experience in signal and power integrity simulations, analysis and optimization for 2.5D and 3D packages including interface with memory, interposer, substrates and PCBs. Ability to determine optimal signal routing, power delivery verification and package size determination Bachelor’s degree in mechanical engineering, material science or related fields and 10+ years of related professional experience or master’s degree and/ or PhD degree / post-doc with 8+ years of experience. Experience interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design. Skills needed to be successful in this role: Ability to develop an idea into a proof of concept and then a proof of concept into a productizable technology Deep understanding of fundamental concepts of signal and power integrity, transmission line and electromigration, and the ability to apply those concepts to create new design rules and explore new technologies utilizing current baseline for 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB-T, (c) CPO, (d) CPC. Mastery in tools and workflows to guide and enable the team on what sims need to be run: previous hands-on experience with signal and power integrity analyses using Cadence Sigrity PowerSI and Ansys SIwave; EM sims using Ansys HFSS, SI-Wave, Cadence Clarity, and the ability to correlate that with real world challenges is a required skill. Good understanding of interposer, substrate, package, PCB level design rules, ability to perform routing feasibility studies using Cadence APD or PCB editor. Good understanding of chip-package interactions and failure mechanism at component and board level, thermal and warpage management. Ability to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe. Ability to influence vendors to align their roadmap with company goals. Strong communication, presentation and documentation skills The ideal candidate would have: Prior experience in data center AI accelerators, networking silicon, or custom HPC silicon. Board, system and rack level integration, thermal, mechanical, signal and power analysis. Ability to influence senior stakeholders across architecture, silicon design, system platform engineering, and supply chain Experience setting roadmaps, not just executing them. Experience with silicon disaggregation and reaggregation and memory integration. Demonstrated leadership driving cross-company supplier programs. Experience with VNA and TDR measurements for package and PCB characterization Experience in advanced package and substrate technologies with understanding of process and materials, component and board level reliability, warpage and thermal management.

Requirements

Experience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management.
Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries.
Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies.
Experience in signal and power integrity simulations, analysis and optimization for 2.5D and 3D packages including interface with memory, interposer, substrates and PCBs.
Ability to determine optimal signal routing, power delivery verification and package size determination
Bachelor’s degree in mechanical engineering, material science or related fields and 10+ years of related professional experience or master’s degree and/ or PhD degree / post-doc with 8+ years of experience.
Experience interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design.
Ability to develop an idea into a proof of concept and then a proof of concept into a productizable technology
Deep understanding of fundamental concepts of signal and power integrity, transmission line and electromigration, and the ability to apply those concepts to create new design rules and explore new technologies utilizing current baseline for 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB-T, (c) CPO, (d) CPC.
Mastery in tools and workflows to guide and enable the team on what sims need to be run: previous hands-on experience with signal and power integrity analyses using Cadence Sigrity PowerSI and Ansys SIwave; EM sims using Ansys HFSS, SI-Wave, Cadence Clarity, and the ability to correlate that with real world challenges is a required skill.
Good understanding of interposer, substrate, package, PCB level design rules, ability to perform routing feasibility studies using Cadence APD or PCB editor.
Good understanding of chip-package interactions and failure mechanism at component and board level, thermal and warpage management.
Ability to manage programs involving cross-functional teams.
Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe.
Ability to influence vendors to align their roadmap with company goals.
Strong communication, presentation and documentation skills

Nice To Haves

Prior experience in data center AI accelerators, networking silicon, or custom HPC silicon.
Board, system and rack level integration, thermal, mechanical, signal and power analysis.
Ability to influence senior stakeholders across architecture, silicon design, system platform engineering, and supply chain
Experience setting roadmaps, not just executing them.
Experience with silicon disaggregation and reaggregation and memory integration.
Demonstrated leadership driving cross-company supplier programs.
Experience with VNA and TDR measurements for package and PCB characterization
Experience in advanced package and substrate technologies with understanding of process and materials, component and board level reliability, warpage and thermal management.

Responsibilities

Develop packaging technology roadmap for AI XPU, XPU-attach and Switch
Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance.
Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization.
Explore technology feasibility and create proof-of-concept samples and productize technologies.
Define package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope.
Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability.
Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis.
Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements.
Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost.
Drive package qualification and reliability validation to volume readiness.