Apple-posted 2 months ago
Sunnyvale, CA
5,001-10,000 employees

As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world! You will learn all aspects of a large-scale SOC, different types of SOC architectures, high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.

  • Verify complex SOCs as part of the Wireless SOC team.
  • Integrate multiple sophisticated IP level DV environments.
  • Craft highly reusable best-in-class UVM Testbenches.
  • Implement effective coverage driven and directed test cases.
  • Deploy new AI tools and implement methodologies to improve quality of tape-out readiness.
  • Collaborate with other product development groups across Apple.
  • Learn all aspects of a large-scale SOC and different types of SOC architectures.
  • Gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture.
  • Responsible for pre-silicon RTL verification of block and top-level SOC.
  • Engage in all aspects of SOC Design Verification engineering.
  • BS degree and a minimum of 10 years relevant industry experience.
  • Proven track record of working full ASIC cycle from concept to tape-out to bring-up.
  • Experience in test-planning, testbench implementation, test sequence creation and debugging, and coverage closure.
  • Expertise in SystemVerilog coding and UVM methodology.
  • Dedicated/hands-on ASIC & SOC DV experience.
  • Experience taping out large SOC systems with embedded processor cores.
  • Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI based bus architecture in UVM environment.
  • Experience with Formal Verification.
  • In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
  • Low Power Verification experience.
  • Excellent communication and problem-solving skills.
  • Desire to seek diverse challenges.
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service