UVM System Verification Engineer IRC258952

Hitachi • Basking Ridge, NJ

276d

About The Position

The UVM System Verification Engineer will be responsible for UVM-based verification or digital design verification. The role requires a basic understanding of System Verilog and Universal Verification Methodology (UVM), along with experience in C/C++ for verification and embedded systems. Familiarity with scripting languages such as Python or Perl for automation and exposure to simulation tools like ModelSim or QuestaSim is also necessary.

Requirements

• Experience in UVM-based verification or digital design verification.
• Basic understanding of System Verilog and Universal Verification Methodology (UVM).
• Experience with C/C++ for verification and embedded systems.
• Familiarity with scripting languages such as Python or Perl for automation.
• Exposure to simulation tools such as ModelSim or QuestaSim.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields.

Responsibilities

• Analyze test results, debug issues, and collaborate with senior engineers to resolve defects.
• Ensure compliance with industry standards and customer requirements.
• Document test procedures, results, and defect tracking.
• Continuously learn and improve test methodologies and verification processes.
• Assist in developing and implementing UVM-based verification plans for FPGA designs.
• Perform functional and regression testing for digital hardware components.
• Develop and maintain test benches, test cases, and automation scripts in System Verilog.

Benefits

• Culture of caring that prioritizes people first.
• Commitment to continuous learning and development.
• Opportunities to work on interesting and meaningful projects.
• Balance and flexibility in work arrangements.
• High-trust organization with a focus on integrity.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Electrical Equipment, Appliance, and Component Manufacturing
• Education Level: Bachelor's degree