In this position you will be delivering compelling timing sign-off methodology to Intel foundry customers and enable best in class PPA on Intel technology. Working closely with EDA vendors, improve and validate flows for industry standard tools used for timing sign-off flow. Develop custom flows for validating EDA tool features. Collaborate with technology leads, VLSI physical design, and timing engineers to understand impact of variation, aging, power delivery network, etc. and deploy nuanced strategies of timing signing off. Work on various aspects of STA, constraints, timing and power optimization.