Timing Engineer/Lead

Altera Semiconductor-posted 14 days ago

Full-time • Mid Level

San Jose, CA

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About Altera Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation. Our innovation in programmable logic began in 1983. Since then we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets. Join us on our journey to becoming the world’s #1 FPGA company! About the Role Altera is looking for a Timing Engineer to lead timing activities for a subsystem. This person will be joining our Physical Design team and will be working/collaborating with the design and architecture team.

Drive timing closure at block level and sub-system level.
Developing methodology through flow/scripting which will result in easier interface timing closure at full chip.
Define and manage I/O timing budgets across hierarchical designs.
Apply advanced sign-off methodologies at lower nodes, including POCV and PVT effects.
Provide actionable timing feedback at both block and sub-system levels, including root cause analysis and ECO guidance.
Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
Global clock planning for easier interface timing closure.
Work closely with design, implementation, and full chip teams to drive timing convergence, providing sign-off level expertise and guidance.

Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred with 7+ years in the following:
7+ years of experience in timing analysis and sign-off.
Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
Experience in synthesis, place-and-route, extraction.
In-depth knowledge of advanced timing concepts in lower nodes (5nm or below).
Proficiency with Tempus/Primetime tools.
Strong scripting ability (Tcl, Python, Perl).
Experience working independently with strong prioritization and solution oriented mindset.

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