Timing Convergence Lead (STA)

Intel Corporation • Austin, TX

2d • Hybrid

About The Position

Intel put the Silicon in Silicon Valley. No one else is obsessed with engineering a brighter future. Every day, we create world-changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are Intel is revolutionizing the Data Center and Server segment. Join us and change the way the world builds servers. Intel's Data Center group is seeking talented and enthusiastic designers to join our growing team and take part in developing state-of-the-art servers that will move data at higher speeds in the Data Center, enriching the lives of every person on Earth. Your Mission as Timing Convergence Lead As our Timing Convergence Lead, you'll be at the forefront of cutting-edge semiconductor design, ensuring our next-generation server processors meet the most demanding performance requirements. You'll drive timing closure across complex, multi-domain designs that power the world's data infrastructure.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field
• 4+ years of experience in Static Timing Anaysis (STA)
• Experience in one or more of the following: OCV/POCV/LVF, MMMC, Clock Tree Analysis, and SI/Noise analysis.
• 4+ years of experience with industry-standard STA tools: Synopsys PrimeTime (preferred) or Cadence Tempus.
• Experience enabling Tweaker/PrimeTime based ECO flows and closure methodologies on complex multi-voltage designs
• Scripting experience i.e. Tcl, Python, or Perl for automation.
• Experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm)
• Deep expertise in digital design implementation (RTL to GDSII) using Synopsys/Cadence tools
• Strong understanding of LVF/POCV variation formats and deep sub-micron design challenges
• Proven experience with constraint development and cleanup
• Knowledge of advanced CTS strategies and timing optimization techniques

Nice To Haves

• Post graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field
• Server design experience - a significant plus!

Responsibilities

• Lead STA Excellence: Drive setup, convergence, reviews, and sign-off for multi-mode, multi-corner, multi-voltage domain designs
• Master Timing Closure: Perform comprehensive timing analysis and closure at Partition/Sub-system/FC levels
• Influence & Collaborate: Drive convergence by partnering with APR and Design teams as a key stakeholder
• Innovate Methodologies: Develop constraint strategies and provide expert feedback on Clock Tree Synthesis (CTS) approaches
• Pioneer ECO Solutions: Lead timing ECO implementation strategy development and enable Tweaker/Prime Time ECO flows
• Automate & Optimize: Create automation scripts within STA tools for methodology advancement
• Solve Complex Challenges: Apply excellent debugging skills to implementation issues with creative, breakthrough solutions
• Evaluate & Advance: Assess multiple timing methodologies and tools across various designs and technology nodes

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level