Technical Staff Engineer - Architecture (SOC)

Microchip • San Jose, CA

16h • $88,000 - $232,000

About The Position

Join our dynamic FPGA (Field Programmable Gate Array) Business Unit as a Technical Staff SOC Architecture Engineer. We are at the forefront of developing SOC FPGA compute platforms for a diverse range of low-power applications, including smart embedded vision, industrial IoT, access/gateways/aggregation networks, and compute platforms for aerospace and defense. As an SOC Architect, you will collaborate with a team of highly motivated architects and senior designers to define and deliver next-generation, power-optimized FPGA solutions.

Requirements

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 10–15 years of industry experience in SOC architecture and design.
• Proven experience developing ARM M-Class or RISC-V Embedded SOC architectures.
• Expertise in SOC advanced interconnect, AMBA, SOC peripherals, and DDR memory.
• Proficiency in developing microarchitecture specifications, RTL design, and logic simulations.
• Hands-on experience with Verilog, Cadence/Synopsys/Siemens simulation environments, synthesis, and DFT insertion EDA tools.
• Strong scripting skills in CSH/BASH, PERL, or Python.
• Demonstrated adaptability and flexibility in a fast-paced, evolving environment.
• Excellent verbal and written communication skills, with the ability to convey complex technical concepts to cross-functional teams.
• Proactive problem-solving attitude and a willingness to take initiative in addressing technical challenges.

Nice To Haves

• Experience in SOC architecture performance analysis, tools, and simulators at various abstraction levels (Cycle Accurate, TLM, and/or Functional).
• Familiarity with UVM and functional coverage methodology.
• Experience with vector processing micro-architectures is a major plus.

Responsibilities

• Lead technical diligence and perform trade-off analysis of product requirements during the Product Concept Phase, translating them into actionable Design Requirements for the Product Definition Phase.
• Collaborate with Embedded Software teams to define optimal Hardware Abstraction Layer (HAL) and driver interfaces, ensuring seamless integration and performance.
• Develop detailed microarchitectural specifications, ensuring accurate capture of design intent, identifying technical gaps, and proposing effective remedies.
• Drive RTL implementation and partner with Logic Verification and ASIC Implementation teams through synthesis and DFT insertion.
• Lead discussions with CPU and IP vendors to shape future features and requirements.
• Develop and utilize techniques and tools for SOC benchmarking and bandwidth analysis, delivering optimized system solutions.
• Work cross-functionally with Functional Verification, ASIC Implementation, and Embedded Software teams across multiple geographical locations.
• Oversee all facets of interconnect to FPGA fabric, associated peripherals, and IO resources, extending beyond the SOC boundary.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments.
• our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level