Technical Director of Systems Engineering
About The Position
MaxLinear is seeking a Technical Director of Systems Engineering to join our team. You will be responsible for architecting and developing cutting-edge hardware platforms optimized for high-performance storage accelerator solutions. This role demands deep expertise in PCIe Gen5/Gen6 protocols, hands-on debugging, and board-level design of PCIe, OCP, and EDSFF form factors. You will drive architecture, design, validation, compliance with industry standards, and support of at scale manufacturing. In this role, you will focus on the following: PCIe Gen5/6 Protocol Expertise & Debugging Serve as the subject matter expert on PCIe Gen5 and Gen 6 protocols and physical layer implementation Conduct hands-on debugging and root-cause analysis for development and field issues Provide guidance on emerging interface technologies such as CXL, UALink, and other high-speed interconnects Hardware Design & Development Lead the design and development of PCIe HHHL, OCP 3.0 NIC, and EDSFF form factor boards for high-volume production Architect and implement high-speed interface designs, including PCIe Gen5 and OCP-compliant protocols Perform comprehensive Power Integrity (PI) and Signal Integrity (SI) analysis to ensure robust board-level performance Testing & Validation Drive Design Validation Testing (DVT) and Production Validation Testing (PVT) processes Develop and execute thermal test plans in collaboration with an internal team as well as third-party thermal labs Compliance & Certification- Ensure hardware designs meet industry standards and certifications including FIPS, RoHS, and other relevant regulatory requirements Manufacturing Support Own and manage Functional Circuit Test (FCT) and In-Circuit Test (ICT) processes Lead RMA analysis and work closely with customers and manufacturing teams to resolve board-level issues
Requirements
- Deep expertise in PCIe Gen5 and Gen6 protocols and OCP standards
- Proven track record of high-speed board design, SI/PI analysis, and board-level debugging
- Experience with compliance testing and certification processes
- Excellent verbal and written communication skills
- BS in Electrical Engineering or related + 13 years of experience, or MS + 11 years of experience, or Ph.D. + 8 years of experience
Nice To Haves
- Familiarity with emerging technologies like CXL and UALink is a strong plus
Responsibilities
- Serve as the subject matter expert on PCIe Gen5 and Gen 6 protocols and physical layer implementation
- Conduct hands-on debugging and root-cause analysis for development and field issues
- Provide guidance on emerging interface technologies such as CXL, UALink, and other high-speed interconnects
- Lead the design and development of PCIe HHHL, OCP 3.0 NIC, and EDSFF form factor boards for high-volume production
- Architect and implement high-speed interface designs, including PCIe Gen5 and OCP-compliant protocols
- Perform comprehensive Power Integrity (PI) and Signal Integrity (SI) analysis to ensure robust board-level performance
- Drive Design Validation Testing (DVT) and Production Validation Testing (PVT) processes
- Develop and execute thermal test plans in collaboration with an internal team as well as third-party thermal labs
- Ensure hardware designs meet industry standards and certifications including FIPS, RoHS, and other relevant regulatory requirements
- Own and manage Functional Circuit Test (FCT) and In-Circuit Test (ICT) processes
- Lead RMA analysis and work closely with customers and manufacturing teams to resolve board-level issues
Benefits
- health care benefits
- 401k savings plan
- Employee Stock Purchase Plan (ESPP)
- paid time off
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What This Job Offers
Job Type
Full-time
Career Level
Director
