Tech Lead, Performance and Power Analysis

Neurophos • Austin, TX

8d • Onsite

About The Position

At Neurophos, listed as one of EE Times’ 2025 100 Most Promising Start-ups, we are revolutionizing AI computation with the world’s first metamaterial-based optical computing platform. Our design addresses the traditional shortcoming of silicon photonics for inference and provides an unprecedented AI engine with substantially higher throughput and efficiency than any existing solution.
We've created an optical metasurface with 10,000x the density of traditional silicon photonics modulators. This enables a solution with 100x gains in power efficiency for neural network computing without sacrificing throughput; we've made improvements there, too. By integrating metamaterials with conventional optoelectronics, our compute-in-memory optical system surpasses existing solutions by a wide margin and enables truly high-performance and cost-effective AI compute.
Join us to shape the future of optical computing.
Location: San Francisco Bay Area or Austin, TX. Full-time onsite position.
Position Overview:
We are seeking an experienced Lead for Performance and Power Analysis (PPA) to establish and drive our modeling infrastructure for performance characterization and power/energy optimization. This leadership role combines deep technical expertise in hardware modeling with team leadership responsibilities. You will build the PPA modeling team, define methodologies for performance and power simulation, and drive critical architectural decisions through data-driven analysis of our novel optical computing platform.

Requirements

• MS or PhD in Computer Engineering, Electrical Engineering, or Computer Science (or BS with equivalent experience)
• 10+ years of experience in performance modeling and power analysis for CPUs, GPUs, or accelerators
• Proven experience building and leading technical teams (3+ years of management experience)
• Deep expertise in discrete-event simulation, cycle-accurate modeling, and performance analysis
• Strong background in power modeling frameworks (McPAT, Cacti, or custom methodologies)
• Expert-level C++ programming with a focus on performance-critical simulation code
• Experience with trace-driven simulation and performance bottleneck analysis
• Track record of shipping performance models that drove silicon design decisions
• Excellent communication skills and ability to present technical results to diverse audiences
• Experience with performance characterization of ML workloads on specialized hardware

Nice To Haves

• Experience with GPU performance modeling or shader core analysis
• Background in accelerator architectures (TPU, NPU, DSP) or domain-specific processors
• Knowledge of memory system modeling (HBM, DRAM controllers, cache hierarchies)
• Familiarity with optical computing, photonics, or analog computing paradigms
• Experience with event-driven simulation frameworks (SystemC, gem5, SST)
• Understanding of ML framework internals (PyTorch, TensorFlow) and workload characteristics
• Background in statistical performance modeling and regression analysis
• Experience with power optimization techniques for datacenter processors
• Publication record in computer architecture or hardware modeling venues

Responsibilities

• Lead the PPA modeling team (4+ engineers) focused on performance and power analysis
• Architect and implement performance models with discrete-event timing and cycle-accurate simulation
• Develop power and energy modeling frameworks for optical engines, SRAM arrays, and digital logic
• Define PPA analysis methodologies and establish modeling best practices
• Drive performance optimization through bottleneck identification and architectural trade-off analysis
• Collaborate with the architecture team on the performance characterization of novel compute blocks
• Build and maintain a trace-driven simulation infrastructure for independent performance analysis
• Develop power models for optical components, photonic devices, and opto-electronic interfaces
• Work with silicon design teams to validate models against RTL and post-layout results
• Mentor modeling engineers and establish team development practices
• Present PPA results to the executive team and drive architecture decisions

Benefits

• A pivotal role in an innovative startup redefining the future of AI hardware.
• A collaborative and intellectually stimulating work environment.
• Competitive compensation, including salary and equity options.
• Opportunities for career growth and future team leadership.
• Access to cutting-edge technology and state-of-the-art facilities.
• Opportunity to publish research and contribute to the field of efficient AI inference.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level