A TD Design Collateral Modeling Engineer is responsible for creating and refining models and data related to the design, including but not limited to CMOS Spice models, NAND array and interconnect RC models.
Model development: design and maintain modeling tiles on test chip and product scribes, perform electrical validations on silicon, generate device and interconnect RC models, calibrate models with corners based on fab process targets and variations.
Cross-functional collaboration: work closely with Device, Design, PI, and Process engineers to solve device and model related issues, meeting NAND performance target, passing technology qualifications.
BS, MS, or PhD in a science or engineering field and minimum 5 years of experience in research or development environment for the relevant technical areas are required
Hands-on expertise in device modeling tools such as Verilog-A or similar simulation platforms
Strong understanding of semiconductor physics, particularly CMOS transistor operation and device scaling principles.
Strong communication and collaboration skills to work effectively with cross-functional teams. The candidate will need to be a collaboration role model, establishing strong technical and personal credibility, ensuring on-time project success through influencing and working with other organizations
Excellent statistical data analysis and problem-solving skills
Hands-on expertise in electrical characterization techniques like IV curves, capacitance-voltage measurements, and device modeling.
Proficiency in TCAD simulation tools for device design and analysis
Experience with semiconductor fabrication processes
Demonstrated technical leadership and a track record of problem solving with creativity and out-of-box thinking