Systems Engineering Intern - Silicon PDK
About The Position
Kilby Labs is seeking a highly motivated and experienced silicon photonics Process Design Kit (PDK) and Layout Engineering Intern to support the development of next-generation photonics design methodologies, with a focus on schematic-driven layout for photonics integrated circuits (PIC) and optical-electrical PDK development. The role will contribute to building a scalable, automated design flows that bridge schematic capture, layout generation, and simulation / testbench infrastructure within a Cadence-based platform. This position offers hands-on exposure to advanced PIC design enablement and electronic-photonics co-design workflows with close collaboration with the silicon photonics designers, RF designers, and layout engineers.
Responsibilities
- Assist in the development of schematic-driven layout flows for PIC, including creating of symbols, layout, ports, and connectivity.
- Translate schematic-level designs into layout and creat Parametric Cells using in SKILL scripting.
- Support design enablement and PDK development, including building and maintaining a PDK and schematic-driven layout automation.
- Contribute to the definition and implementation of design rules and verification methodologies, including design rule check (DRC) and layout versus schematic (LVS) checks for connectivity and netlist validation.
- Support optical-electrical co-design by linking photonic and RF blocks using Verilog-A behavior models and S-parameters for system-level simulation.
- Collaborate with cross-functional teams to validate flows through integrated simulation and testbench development
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What This Job Offers
Career Level
Intern
Education Level
No Education Listed
