System Power Engineer, Principal

d-Matrix • Santa Clara, CA

1d • Hybrid

About The Position

As the Principal System Power Engineer, you will be the lead architect for the energy backbone of our AI accelerators. This role is unique in its breadth, spanning from the MCM (Multi-Chip Module)/Chiplet-level power distribution through the PCBA and into the system-level power shelf. You will solve the formidable challenge of delivering thousands of amps to high-performance silicon while maintaining razor-sharp power integrity. You aren't just managing power; you are engineering the efficiency and stability that makes large-scale AI inference possible.

Requirements

• BS/MS/PhD in Electrical Engineering or a related technical field.
• 12+ years of experience in power electronics and system-level power delivery for HPC, GPUs, or Data Center hardware.
• Expert knowledge of DC-DC converter topologies (Buck, Multiphase, TLVR).
• Deep understanding of PDN modeling and simulation (e.g., Ansys SIwave, Cadence Sigrity/CST).
• Experience with high-current transients (di/dt) associated with 5nm/3nm process nodes.
• Proficiency with high-speed scopes, electronic loads, and FRA (Frequency Response Analyzers) for Bode plot and impedance measurements.
• Proven track record of designing power for complex packages or multi-die modules.

Nice To Haves

• Familiarity with Vertical Power Delivery (VPD) or back-side power delivery technologies.
• Experience with 48V-to-12V intermediate bus conversion and Open Compute Project (OCP) power specifications.
• Understanding of PMBus/I2C/SVI3 protocols for telemetry and power management.

Responsibilities

• Architect end-to-end power delivery solutions for high-TDP AI accelerators, focusing on multi-phase VRMs (Voltage Regulator Modules) and Point-of-Load (PoL) converters.
• Lead the definition of power delivery for chiplet-based architectures, including substrate PDN, micro-bump current density analysis, and transient response optimization at the die-to-die interface.
• Drive the PI strategy across the board and package. This includes performing/overseeing DC drop analysis, AC impedance profiling (Z_target), and decoupling capacitor optimization to mitigate high-frequency noise.
• Partner with the Hardware Qualification and SI/PI teams to define validation suites. You will lead the correlation between simulation results and lab measurements using specialized tools like power emulators and high-bandwidth probes.
• Drive technical requirements and design reviews with ODM partners, ensuring that outsourced PCBA designs meet d-Matrix’s stringent power efficiency and noise floor standards.
• Collaborate with thermal engineers to optimize the layout for heat dissipation while maintaining low-impedance power paths.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: Ph.D. or professional degree
• Number of Employees: 101-250 employees