Cirrus Logic is seeking a creative and hardworking engineering intern to join our outstanding Analog/Mixed-Signal Verification, Modeling and Methodology Team. You will collaborate with systems and design teams to facilitate tops down design methodology through the development and validation of System Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This internship will take place during the Summer 2026 semester over the course of a 12-14 week long internship working a full-time schedule.