Substrate Layout Designer

ZP Group•Saratoga, CA

32d•$148,000 - $168,000•Onsite

About The Position

Piper Companies is seeking a Substrate Layout Designer to join a fast-growing innovator in AI infrastructure, for an onsite 4-6 month contract position in Saratoga, CA. The Substrate Layout Designer will play a critical role in making sure high-performance chips-used in AI, data centers, and advanced computing-can actually be built and work reliably.

Requirements

8+ years of hands-on experience in substrate layout design for high-performance semiconductor packaging, including multi-die or chiplet-based architectures.
Proficiency with advanced layout tools, including Allegro Cadence APD and AutoCAD, with a strong understanding of design rule checks (DRC), manufacturability (DFM), and fabrication constraints.
Deep knowledge of substrate technologies such as organic substrates, fine-pitch bump escape routing, and constrained layer stack-ups.
Familiarity with signal and power integrity principles, and how physical layout impacts electrical performance in high-speed, high-density designs.
Strong collaboration and communication skills, with a proven ability to work across engineering disciplines and with external manufacturing partners.

Responsibilities

Helping to lead the physical layout design of high-density substrates for advanced multi-die packages, including planning bump maps, escape routing, and layer stack-ups.
Collaborate with cross-functional engineering teams (e.g., electrical, mechanical, signal/power integrity) to ensure alignment between chip floorplans, system constraints, and packaging requirements.
Utilize industry-standard design tools to create, validate, and optimize substrate layouts, ensuring compliance with design rules and manufacturability standards.
Conduct design reviews and interface with manufacturing partners to support tape-out, fabrication readiness, and iterative improvements.
Ensure electrical performance and reliability through intelligent routing strategies and adherence to signal and power integrity best practices.