Static Timing Analysis (STA) Engineer – (Lead or Senior)

Boeing • El Segundo, CA

1d • $146,200 - $239,200 • Onsite

About The Position

Static Timing Analysis (STA) Engineer – (Lead or Senior) Company: Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Static Timing Analysis (STA) Engineer to join us as part of our Boeing Electronic Products team located in El Segundo, CA and at the heart of Boeing’s products - ASICs and FPGAs. Our Electronics Products team goal is to be Boeing’s sole source for electronics. We’ve grown by over 400% and continue to have new opportunities to support more Boeing Platforms. We are seeking an experienced Static Timing Analysis Engineer that is ambitious and will thrive in a technology development environment and can work the full spectrum from research through flight insertion. We’re highly supportive of innovative thinking, we respect and acknowledge hard work, we recognize maturity and integrity, and we reward bottom-line achievement. At Boeing, we value your curiosity, your determination, and your imagination. #TheFutureIsBuiltHere The work we do enables the missions and needs of our customers as we help Connect, Protect, Explore, and Inspire the world. Our team of engineers leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. Plus, we're applying the latest digital IC design processes with industry-best tools to enable applications that cut across every domain at Boeing. Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As a Static Timing Analysis (STA) Engineer you will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on the most critical programs across the Boeing Defense and Security enterprise. You will collaborate with other electronics groups across the company and around the world from the early design stages until signoff to help achieve first pass success. You will be working with a large physical design team within the company and outside of the company for timing convergence. Boeing STA engineers are required work with IP team, EDA vendors, and Foundry for the design closure.

Requirements

• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
• 5 years of experience with timing closure on ASICs and FPGAs
• Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out.
• Good understanding of RTL to GDS flow
• Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
• Ability to work with large physical design team to make the timing convergence successful

Nice To Haves

• Lead, Level 5: 15+ years of related work experience or an equivalent combination of education and experience
• 10 or more years of experience with timing closure on ASICs and FPGAs
• Completed multiple first-pass success ASIC tape-outs with intricacies (Cross clock domain, async crossing etc.)
• Experience in using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)
• Fair knowledge of Synopsys Fusion Compiler, Formality (Cadence LEC), and other relevant tools (e.g. TCM, Fishtail)
• Synopsys physical design AI tool experience is a plus
• Experience leading static timing closure and training new hires
• Familiarity with space-based design techniques and radiation mitigation
• Understanding of design for testability (DFT) and its implications on timing
• Capable of working independently, self starter
• Proficiency with multiple scripting languages (Python, C SHELL, TCL)
• Capable of handling timing closure on multiple designs simultaneously

Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle
• Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
• Facilitate STA methodology in collaboration with other STA leaders
• Generate timing constraints for multiple ASICs and FPGAs
• Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
• Responsible for intricate cross domain timing path closure
• Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
• Programming skills with Python, TCL, Perl, Unix shell etc.
• Help train new engineers

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees