Standard Cell Design Methodology u0026 Flow Engineer

Apple Inc.-posted about 1 month ago
Full-time • Mid Level
Santa Clara, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas and determine how to turn them into reality! You will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking and groundbreaking ideas to the real world. You'll help design the tools that allow us to bring customers experiences they've never-before envisioned. We have an extraordinary opportunity for Standard Cell Design Methodology and Flow Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering quality products to market quickly.Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of talent engineers. In this role on our custom circuits team, you will:

  • Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements.
  • Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows
  • Implement sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification.
  • Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality issues in large datasets.
  • At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc.
  • Experience with timing modeling of large custom macros and complex sequential flops.
  • Exposure to Design For Test, scan concept and write DFT friendly RTL
  • Understands all aspects of implementation specification, design, timing, power, and flow automation.
  • Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation
  • Flow automation skills in standard cells development and integration to improve execution efficiency. Experience of using Python/TCL/Perl
  • Knowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for characterization, synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
  • Proven understanding of device physics and process.
  • Familiar with foundry ecosystem and benchmarking practice.
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