Standard Cell Design Methodology & Flow Engineer

Apple • San Diego, CA

2d

About The Position

Imagine yourself at the center of our cutting-edge processor design in deep
submicron technologies, and on standard cell library designs. You will have the
opportunity to integrate and come-up with new insights, as well as work with a
team of talent engineers. In this role on our custom circuits team, you will: -
Be the interface to internal CAD team for planning production flows and with
foundry on PDK requirements. - Collaborate with technology team on new process
requirements and work with design/CAD team to enable relevant tools/flows -
Implement sophisticated digital block in Verilog/SystemVerilog, run simulations
or formal check for verification. - Use data analysis techniques and/or
sophisticated Machine Learning models to study the circuit trends in timing,
power, and area, and to potentially detect quality issues in large datasets.

Requirements

• BS and a minimum of 10 years of relevant industry experience

Nice To Haves

• At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc.
• Experience with timing modeling of large custom macros and complex sequential flops.
• Exposure to Design For Test, scan concept and write DFT friendly RTL
• Understands all aspects of implementation specification, design, timing, power, and flow automation.
• Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation
• Flow automation skills in standard cells development and integration to improve execution efficiency.
• Experience of using Python/TCL/Perl
• Knowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for characterization, synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
• Proven understanding of device physics and process.
• Familiar with foundry ecosystem and benchmarking practice.

Responsibilities

• Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements.
• Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows
• Implement sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification.
• Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality issues in large datasets.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees