Staff Static Timing Analysis Lead, Cloud

Google-posted 8 days ago

Full-time • Mid Level

Sunnyvale, CA

5,001-10,000 employees

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In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Static Timing Analysis (STA) Lead, you will lead timing margin derivation, constraint development and validation, and timing closure of large, high performance compute Application-specific integrated circuits (ASICs). You will develop static timing methodologies, margins, automation scripts, and write documentation. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to fully implement cross-functional design requirements. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Lead effort for timing constraint creation and validation, timing analysis and timing Engineering Change Order (ECO) creation, and final timing sign-off for ASICs.
Drive both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
Interface with the broader team to triage and resolve reported technical issues, escalating tool-related problems to Electronic Design Automation (EDA) vendors and delivering timely and effective solutions.
Lead collaboration with RTL design and DFT team for high quality integrations and timing constraints.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field or equivalent practical experience.
8 years of experience with Static Timing Analysis (STA) activities, including project planning, scheduling, task allocation, and progress tracking for SOC projects.
Experience in the analysis and cross-chip clock distribution networks.
Experience with Electronic Design Automation (EDA) tools (e.g., Primetime, Tempus, Timevision, STAR-RC) including their technical commands for timing analysis, timing closure, parasitic extraction, noise glitch, and cross-talk.
Experience in achieving full-chip timing convergence and authoring, reviewing, and validating timing constraints (SDC) across designs.

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
12 years of experience in Static Timing Analysis.
5 years of experience in leading STA activities for SOC.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Knowledge of semiconductor device physics and SPICE simulation and full-chip static timing topics.
Ability to deliver on-time STA sign-off and chip delivery including STA flow/methodology, STA flow ownership, timing constraint validation, and timing ECO implementation to achieve successful tape-outs and shipping silicon.

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