Staff/ Sr. Staff Design Verification Engineer - QGOV

Qualcomm • San Diego, CA

68d • $164,000 - $246,000

About The Position

Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to join our Engineering Group, specifically in ASICS Engineering. The role involves familiarity with RTL design in Verilog and System Verilog, developing verification methodologies, and ensuring a scalable and portable environment across simulation and emulation. The engineer will be responsible for developing test plans to verify hardware building blocks, design macros, and standard interfaces such as PCIE, DDR, USB, I2C, and SPI. The position requires ownership of end-to-end DV tasks, including coding test benches and test cases, writing assertions, running simulations, and achieving all coverage goals. The engineer will also explore innovative DV methodologies to continuously enhance the quality and efficiency of test benches and maintain the emulation environment to collect relevant metrics. This position requires full-time presence in San Diego, five days a week, and applicants must be U.S. citizens eligible for government security clearance.

Requirements

• 5+ years of work experience with RTL/FPGA design (Verilog) and embedded system architecture.
• 5+ years of Design Verification, Emulation, and Debug experience with simulation and emulation.
• Relevant experience of 5+ years in Design/Verification/Implementation.

Nice To Haves

• Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
• Strong System Verilog/UVM based verification skills.
• Good understanding of chip-level functional model building.
• Experience in HVL such as System Verilog, UVM/OVM & System C.
• Experience customizing and debugging make-based build flows with Xilinx’s Vivado tools.
• Experience with cm tools such as Git and Gerrit.
• Experience in formal/static verification methodologies.
• Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.
• Experience with synthesizing and optimizing designs in synthesizable Verilog.
• Experience with C/C++ DPI transactors and monitors.
• Experience with debugging tools such as JTAG and lab test equipment.

Responsibilities

• Develop verification methodology ensuring scalable and portable environment across simulation and emulation.
• Develop test plans to verify hardware building blocks, design macros, and standard interfaces.
• Own end-to-end DV tasks from coding test benches and test cases to running simulations.
• Explore innovative DV methodologies to enhance quality and efficiency of test benches.
• Develop and maintain emulation environment to collect metrics related to emulation.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Comprehensive benefits package designed to support success at work, home, and play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees