Staff Process Integration Engineer, APTD

Micron Technology • Boise, ID

1d

About The Position

As a Staff Process Integration Engineer in APTD at Micron, you will own the end‑to‑end integration of next‑generation package architectures: 2.5D, 3D stacking, HBM memory integration, and hybrid bonding. You’ll lead new advanced packaging technology development, technology transfer, design DOEs, analyze yield and reliability, and coordinate across device, design, process, equipment, test, and manufacturing teams to deliver high performance multi‑die technology. The role will operate in a cleanroom environment in full gowning, adhering to EHS/cleanroom protocols. The role may require occasional travel to TD sites in Asia for integration development and transfer support.

Requirements

• BS or MS in Materials/Chemical Engineering
• 6+ years in semiconductor technology development with cleanroom experience
• Hands‑on knowledge of advanced interconnects and bonding flows
• Proficiency in DOE/SPC and data analysis (JMP/Minitab/Python) with demonstrated root‑cause problem solving and yield improvement
• Experience with metrology; SAM, X‑ray/CT, IR, warpage profilers (shadow moiré/DIC)
• Strong communication and technical writing skills with the ability to lead cross‑functional teams and drive action in fast‑paced environments
• Direct experience with hybrid bonding integration and reliability (W2W/C2W)
• Warpage modeling and inline correlation experience

Responsibilities

• Own package‑level process integration across 2.5D/3D flows (wafer-to-wafer, chip-to-wafer, advanced interconnects), defining specs and process windows that meet high performance targets for HPC/AI products
• Develop and integrate semiconductor manufacturing processes. Design, optimize, and implement fabrication flows that seamlessly integrate multiple steps, including lithography, etch, deposition, diffusion, CMP, and thin films, into cohesive production processes.
• Analyze yield, performance, and defect data to root-cause process weaknesses, yield issues, and tool variances; Employ SPC and advanced analytics.
• Lead technology transfer from TD to TD and HVM, establishing mask rules, materials, tool readiness, baseline qualification, and technology validation plans
• Design and execute experiments (DOEs) on bonding, underfill, molding, stacking, and integration steps. Apply SPC to parametrics and yield detractors, validate new materials, design rules to improve yield and device performance, and close the loop with corrective actions.
• Manage hybrid bonding (Cu‑Cu + dielectric) integration. Set surface prep, planarity, and alignment requirements. Qualify W2W/C2W flows and track defectivity and reliability.
• Optimize underfill, TC bonding windows, and pillar/bump geometries for high‑I/O assemblies
• Co‑optimize TSV/interconnect routing and thermal paths to meet bandwidth/latency targets, aligning package floorplans with chiplet partitioning
• Predict and mitigate wafer/die warpage engineering via modeling, cure‑shrinkage controls, and material/process levers; Validate with inline metrology.
• Leverage metrology and inspection skills to deploy SAM, IR microscopy, and emerging XRD warpage mapping to correlate processes, defects, and reliability

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees