ARM-posted 3 months ago
$191,100 - $258,500/Yr
Hybrid • San Diego, CA
5,001-10,000 employees
Professional, Scientific, and Technical Services

Are you passionate about shaping the future of chip design? In the Solutions Engineering group at Arm, we offer the outstanding opportunity for an experienced Power Analysis Engineer to join our successful team in a dynamic and diverse role! Arm is establishing teams to develop new and best-in-class silicon platforms, addressing markets such as premium mobile, compute, IoT, AI/ML server, and automotive. Arm's ambition is to demonstrate efficient performance by architecting, implementing, and fabricating pioneering silicon using the latest SoC process nodes and packaging technologies. This is an exciting and unique initiative, where we are driving how the next generation of leading compute devices are built across the industry. Join Arm to be part of the solution.

  • Analyze and optimize the performance per watt of next generation solutions using innovative technologies, methodologies and tools.
  • Simulation, emulation, modeling and collaboration with cross-functional teams in design, verification, architecture, SW, and pre and post silicon test.
  • Build and innovate new processes.
  • Ensure customer requirements in PPA are measured and analyzed.
  • Develop RTL simulator and emulator-based workloads for power estimation.
  • Create visualizations demonstrating the hardware power signature and capabilities.
  • Review the quality and accuracy of data produced by the latest EDA power analysis tool flows and evaluate new tools and methodologies.
  • Experience in power analysis, modeling or valuable transferable skills from design, implementation, or verification backgrounds.
  • Understanding of low power design features and techniques, including clock and power gating, voltage/frequency scaling, memory/logic retention.
  • Ability to balance trade-offs between power, performance, and area.
  • Verilog or System Verilog experience.
  • Experience using tools for power analysis, power delivery and signoff (e.g. PowerPro, PrimePower, PowerArtist).
  • Knowledge of Physical Implementation flow from RTL through Synthesis, Place & Route to STA.
  • Development or analysis of CPU, Graphics, and Memory benchmarks for PPA analysis.
  • Background in running simulation/emulation tools (e.g. VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc).
  • Competitive compensation structure
  • PTO
  • Sabbaticals
  • Parental bonding leave
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