Staff Physical Design Engineer

PowerLattice Technologies Inc•Chandler, AZ

7d•Hybrid

About The Position

We are seeking a highly skilled Staff Physical Design Engineer to drive the implementation of complex SoC designs from netlist to tapeout. This role requires deep expertise across all aspects of physical design, including floorplanning, power planning, place-and-route, and physical verification, with strong ownership of design quality, schedule, and signoff closure.

Requirements

8+ years of experience in physical design for advanced SoCs
Strong hands-on expertise in: Floorplanning and power planning (including analog/ESD integration) Place-and-route flows (placement, CTS, routing, ECOs) Physical verification (DRC, LVS, antenna) and signoff closure
Solid understanding of: Timing analysis and closure techniques Signal integrity, IR drop, and electromigration considerations Advanced technology nodes and design rules
Experience with industry-standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2, Calibre)
Strong problem-solving skills and ability to debug complex layout issues

Nice To Haves

Experience with mixed-signal SoCs and analog/digital co-design
Experience with power integrity analysis tools
Track record of successful tapeouts in advanced nodes

Responsibilities

Develop and own chip-level and block-level floorplans, including macro placement and partitioning
Define and implement power distribution networks, including digital power grid creation
Integrate and ensure robust power connectivity for analog blocks and ESD structures
Optimize floorplan for performance, congestion, and power integrity
Perform and manage special routing for sensitive analog signals, ensuring signal integrity and isolation
Collaborate closely with analog designers on layout constraints, shielding, and noise mitigation
Ensure proper integration of analog macros within digital environments
Execute standard cell placement, optimization, and congestion management
Perform clock tree synthesis (CTS) and clock optimization
Drive global and detailed routing with focus on timing, SI, and manufacturability
Implement timing and functional ECOs to achieve design closure
Run and analyze physical verification flows including DRC, LVS, and antenna checks
Debug and resolve all layout violations to achieve clean signoff
Work with foundry decks and ensure compliance with process rules
Drive timing closure across all corners and modes
Collaborate with STA teams on setup/hold closure and constraint validation
Optimize design for PPA (power, performance, area) targets