Staff Physical Design Engineer

Analog Devices•San Jose, CA

17h•Hybrid

About The Position

We are seeking a Staff Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team. In this role, you will lead the physical design, timing closure, and sign-off for complex, hierarchical eFPGA fabrics implemented on advanced technology nodes. You will work extensively with Cadence digital implementation tools and Siemens Calibre to ensure robust, high-quality, silicon-proven IP.

Requirements

B.S./M.S. in Electrical or Computer Engineering with 8+ years of experience in physical design.
Expert proficiency with Cadence tools: Genus – synthesis and constraint management Innovus – floorplanning, placement, CTS, routing, and optimization Tempus – timing analysis and closure Voltus – power and EM/IR verification
Hands-on experience at 16nm/7 nm/5 nm or lower nodes, including hierarchical and multi-voltage design.
Strong understanding of UPF-based low-power flows, MCMM analysis, and timing sign-off.
Skilled in Tcl and Python scripting for automation and tool integration.
Proven track record of driving IP-level RTL-to-GDSII implementation with tight PPA targets.
Experience with Calibre DRC/LVS for foundry sign-off.

Nice To Haves

Background in FPGA/eFPGA architecture, routing fabrics, or programmable logic optimization is a Plus
Experience with timing model generation, hierarchical design abstraction, and SoC IP integration.
Exposure to flow development, CAD automation, or methodology ownership is a plus.

Responsibilities

Execute Custom power grid planning, Custom Floorplanning , EM/IR analysis, and coordinate with power and packaging teams for full-chip integration.
Own end-to-end Hierarchical physical implementation of eFPGA IP blocks — including fabric tiles, interconnect networks, and control logic.
Drive all major phases of the RTL-to-GDSII flow using Cadence Genus, Innovus, Tempus, and Voltus.
Perform detailed placement, CTS, routing, and optimization for timing, power, and area closure.
Conduct clock-tree synthesis and multi-corner multi-mode (MCMM) timing analysis to achieve sign-off quality convergence.
Automate design flows and develop Tcl/Python scripts to enhance PnR efficiency and reproducibility.
Perform final sign-off analysis: Tempus for STA and ECO closure Voltus for power/IR verification Calibre for DRC/LVS and physical verification
Collaborate closely with RTL, architecture, and CAD methodology teams to optimize design quality and flow robustness.
Support post-silicon correlation and continuous improvement of physical implementation flows.