Staff Physical Design Engineer

Lightmatter•Mountain View, CA

16h•$195,000 - $214,000•Hybrid

About The Position

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of complex digital blocks. In this role, you will leverage your expertise in advanced process nodes (3nm) to drive timing closure, power integrity, and physical verification for high-performance ASICs. Beyond standard digital flows, you will have the unique opportunity. To work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the photonics industry! If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team!

Requirements

Bachelor’s in Electrical Engineering or Computer Engineering
At least 8+ years of industry experience working as a Physical Design Engineer
Must have completed blocks or top level physical design for large ASICs or mixed signal chips that taped out
Thorough knowledge of timing closure, LVS/DRC closure
Experience in TCL and Python (or other scripting languages)
Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields
Ability to react to change and thrive in a fast paced environment

Nice To Haves

Masters Electrical Engineering or Computer Engineering
Hands-on experience with Cadence tools
Tape-out experience 3nm designs

Responsibilities

Implement digital blocks in advanced tech nodes from synthesis through physical verification, using industry standard tools and flows
Understand and debug timing constraints, derates and margins. Review signoff STA reports and fix timing violations for all timing scenarios
Build and customize power grid and ensure power integrity goals are met
Understand clock details and be able to customize clock implementation for functional and test clocks
Debug and clean up DRC/LVS
Functional and timing ECO implementation
Be willing to do manual layouts as well as willingness to learn and do silicon photonics layout
Work with EDA companies to resolve any tool issues
Write TCL, Python, or Shell scripts to automate flow or customize existing flows