Staff Physical Design Engineer

Marvell•Santa Clara, CA

33d•Onsite

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Custom Cloud Solutions Business Unit (CCS) develops cutting-edge semiconductor solutions in the most advanced technologies. Our focus is on solving the most difficult design problems in the areas of AI, data movement, memory/storage, switch, networking, security, and other infrastructure applications. Your tasks will include performing synthesis, place and route, clock tree synthesis, routing, power-signal integrity, and physical verification as well as timing analysis and closure on multiple intermediate and complex logic blocks with IP challenges. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. This role will expose you to partition and chip-level issues to resolve. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell The Marvell Physical Design team is located in our Santa Clara, CA office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology.

Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related fields and at least 1-3 years of related professional experience or Master's degree in Computer Science, Electrical Engineering or related fields or equivalent professional experience in lieu of a formal degree.
Candidate should have good knowledge on PnR and have handled complex blocks using latest technology nodes like 7nm, 5nm, 3nm
Should have exposure in multiple tool usage across Cadence/Synopsys platforms: Innovus/FC
Knowledge of static timing analysis and synthesis
Skilled knowledge on scripting language i.e. Python, Tcl, Perl
Effective communication, verbal, and written skills

Nice To Haves

Partition-level / multi-hierarchy experience is a plus

Responsibilities

performing synthesis, place and route, clock tree synthesis, routing, power-signal integrity, and physical verification
timing analysis and closure on multiple intermediate and complex logic blocks with IP challenges
developing and implementing timing and logic ECOs
collaborating closely with the RTL design team to drive modifications that address congestion and timing issues
resolve partition and chip-level issues