About The Position

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.   Qorvo’s fast-growing Power Management division, focused on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IOT and Industrial applications, is looking for an experienced Top-level Design Verification Engineer to create next generation and world-class designs in power management solutions.

Requirements

  • Advanced degree in Electrical Engineering or a related field, with strong focus on mixed-signal circuit design and verification.
  • 10+ years of experience in AMS design or verification of analog and power-management ICs.
  • Proficiency in UVM environments, including test cases, coverage models, and global checkers.
  • In-depth knowledge of power-management building blocks such as LDO, Amplifiers, Bandgaps, DCDC regulators, Oscillators, and asynchronous state machines.
  • Excellent problem-solving and debugging skills
  • Effective communication and collaboration skills.
  • Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, silicon debug

Nice To Haves

  • Experience in Top-Down Design MethodologyProficiency in shell or Python scriptingFamiliarity with SV-UDN/EENET modeling techniques.
  • Experience with both GUI and command-line simulation flows.
  • Proficiency with SV Assertions and Functional coverage.Understanding integration of AI into a verification workflow

Responsibilities

  • Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
  • Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use-case.
  • Develop constrained random tests and automated checkers within our TLDV UVM environment.
  • Build high performance, accurate RNM, or VerilogAMS models to support TL simulation.
  • Collaborate with design team to resolve issues identified during verification.
  • Partner with internal design and test teams to ensure device first-pass testability.
  • Continuously improve and align verification methodologies with industry best practicesAutomate verification tasks where applicable.
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