Staff Engineer, Physical Design

Marvell Technology-posted 4 months ago
$105,470 - $158,000/Yr
Full-time • Mid Level
Santa Clara, CA
5,001-10,000 employees
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As a Staff Engineer, Physical Design at Marvell Technology, you will be a key part of a highly skilled global team focused on designing next-generation optical module chips for the high-performance computing AI/ML architecture space. Our custom DSP solutions power critical infrastructure in markets such as data center, connectivity, and optical module. You will work at the forefront of advanced CMOS process technology, contributing to both physical design and the development of efficient design methodologies.

  • Perform synthesis, floor planning, place and route, clock tree synthesis, PGV, and timing analysis on complex blocks.
  • Ensure that designs meet performance, power, and area goals across advanced technology nodes like 5nm, 3nm, and 2nm.
  • Work on Place and Route methodology for efficient and robust design processes, enhancing Marvell’s physical design flow.
  • Maintain and support methodologies to ensure continued improvements in efficiency and accuracy.
  • Develop and implement timing and logic Engineering Change Orders (ECOs) while closely collaborating with RTL teams.
  • Work closely with the frontend design and global timing teams to resolve block-level timing issues.
  • Tackle complex, multi-disciplinary challenges and drive technology advancements in optical DSP chip designs.
  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
  • At least 2 years of related experience in physical design, with a proven track record of successful tape-outs.
  • Experience with advanced technology nodes such as 5nm, 3nm, or below is highly desirable.
  • Strong experience with industry-standard EDA tools, including synthesis, floor planning, place and route, clock tree synthesis, timing closure, EMIR, and physical verification.
  • Proven experience working with RTL-to-GDS flows, including experience with digital logic and computer architecture using Verilog/VHDL.
  • Demonstrable proficiency in scripting languages such as Perl, tcl, and Python for automation and workflow enhancement.
  • Excellent communication skills and a proven ability to work effectively in a collaborative, team-oriented environment.
  • Experience with chiplet-based architectures and full-chip physical design.
  • Experience in static timing analysis (STA), with a focus on timing closure.
  • Familiarity with timing analysis and congestion resolution.
  • Flexible time off
  • 401k
  • Year-end shutdown
  • Floating holidays
  • Paid time off to volunteer
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