Staff Engineer, Physical Design LEC

Tenstorrent

171d • $100,000 - $500,000

About The Position

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation AI hardware, combining innovations in software, compilers, and RISC-V CPU design. Our team is passionate about performance, efficiency, and solving complex problems in silicon and systems. We’re looking for a Physical Design Engineer – LEC & Implementation to join our silicon team. You’ll own logical equivalence checking and support physical implementation tasks including synthesis, PnR, and timing closure—ensuring design correctness and tapeout readiness. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

• 5+ years of experience in physical design, with hands-on LEC ownership.
• Strong understanding of RTL design, synthesis, and equivalence checking.
• Proficiency with physical implementation tasks such as floorplanning, timing closure, I/O planning, and power optimization.
• Experience using industry-standard EDA tools for synthesis, PnR, LEC, and timing (e.g., Synopsys, Cadence, Siemens).
• Solid scripting skills (Python, TCL, Perl) to build automation and improve design efficiency.
• Familiarity with ECO flows, and block- or chip-level timing closure on successful taped-out designs.

Responsibilities

• Own logical equivalence checking and support physical implementation tasks including synthesis, PnR, and timing closure.
• Ensure design correctness and tapeout readiness.
• Debug complex implementation or verification mismatches and provide actionable insights.
• Collaborate effectively across disciplines.

Benefits

• Highly competitive compensation package including base and variable compensation targets.
• Equal opportunity employer.

What This Job Offers

• Career Level: Entry Level
• Number of Employees: 501-1,000 employees