The Staff Digital Verification Engineer will join PsiQuantum's Electronic Sub-Systems team in the verification of innovative digital microarchitecture implementation for FPGAs and ASICs.
Development and ownership of DV (design verification) testbench, including checkers, monitors, scoreboards, assertions and functional coverage.
Develop test plan and test cases to cover design feature set. This involves planning the verification of complex digital design blocks, understanding the design specification, and interacting with design engineers to identify important verification scenarios.
Work closely with design teams on failure debug, code coverage and functional coverage closure.
Debug regression failures and identify bug fixes.
Creating documentation and reports.
Degree in computer engineering, electrical engineering, computer science, or related field. MS preferred.
12+ years industrial experience in related fields.
Experience with SystemVerilog.
Experience in verification and general design and verification concepts.
Experience in developing Monitors, Scoreboards and Sequencers that utilize SystemVerilog and UVM.
Ability to create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
Experience in Silicon bringup.
FPGA experience.
Experience in scripting languages such as Python.
Understanding standard bus protocols like AXI, SPI, I2C would be a plus.
Ability to collaborate effectively across departments, sites, and time zones and adapt to dynamic environment.