Staff DFT STA Constraints Engineer

ARM-posted about 2 months ago
Full-time • Mid Level
San Diego, CA
5,001-10,000 employees
Professional, Scientific, and Technical Services
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Arm's Solutions group DFT team implements DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We closely collaborate with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. We are currently hiring across three locations: San Jose, Austin, and San Diego.

  • Lead DFT design and STA constraints to meet design PPA targets.
  • Coordinates DFT requirements across SOC, IP and product teams.
  • Architect, implement, and validate innovative DFT techniques on SOCs and sub-systems.
  • Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools.
  • Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
  • Participate in ATE targeted test patterns, validation and silicon- debug
  • Work closely Test and product engineering teams on silicon characterization and validation.
  • This role is for a Principal DFT Engineer / DFT STA Constraints Lead with 10+ years of experience in Design for Test.
  • Understanding DFT timing signoff modes and constraints and familiarity with Synthesis and Static Timing Analysis.
  • Experience in validating and supporting DFT timing constraints in Geuns, Innovus, Fusion compiler, and PrimeTime.
  • Core DFT skills considered crucial for this position should include some of the following: experience in Siemens DFT tool, DFT timing constraints, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
  • Experience coding Verilog RTL, TCL and/or Perl
  • Familiarity with SoC style architectures including multi-clock domain and low power design practices.
  • Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
  • Backgournd in high performance design, implementation and timing convergence is a plus
  • Experience with 2.5D and 3D test
  • Experience with Cadence, and/or Synopsys DFT and simulation tools
  • Ability to work both collaboratively on a team and independently.
  • Innovative and a passion for progress
  • Hard-working and excellent time management skills with an ability to multi-task
  • An upbeat approach to working on ambitious projects on the cutting edge of technology
  • Communicate optimally across teams and sites in different geographies and time zones
  • Good analytical and debug skills with a "figure it out" mentality
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