Staff Design Engineer (Low Power)

Qualcomm•Santa Clara, CA

About The Position

Qualcomm-Atheros, a.k.a. QCA, is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast paced Integrated Wireless Technology team, you will be working on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction techniques. The candidate will be responsible to develop technical specifications from Architectural and systems requirements and deliver detailed low power micro-architecture and design. Also work closely with verification team to develop verification plans and actively participate in debug phase. The candidate will work hands-on and own their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is also responsible for the silicon power measurements, Si debug and power correlation. The candidate will also be responsible for the full chip debug design using ARM IPs.

Requirements

Experience in SoC low power micro-architecture, low power design and methodology, Power Intent/Implementation, power estimates, power analysis tools and power reduction techniques is a must.
Experience in silicon bring up and debug is a must.
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

Experience in ARM IP based full chip debug is preferred.
7+ yrs. of working experience in ASIC Design.
Low power micro-architecture, Design, Power Intent/Implementation, power optimization and power estimation is preferred.
Experience on SoC micro architecture, multi-domain clocking, AMBA bus protocols such as AHB and APB. AXI is preferred.
Experience in PCIE/USB peripherals is preferred.
Experience in CPU sub system-based design is preferred.
Experience in low power design from project start to volume chip production for at least one product cycle is preferred.

Responsibilities

Develop technical specifications from Architectural and systems requirements and deliver detailed low power micro-architecture and design.
Work closely with verification team to develop verification plans and actively participate in debug phase.
Work hands-on and own their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up.
Responsible for the silicon power measurements, Si debug and power correlation.
Responsible for the full chip debug design using ARM IPs.