Staff ATE Test Engineer

indie Semiconductor-posted 6 months ago

Mid Level

Aliso Viejo, CA

Computer and Electronic Product Manufacturing

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As a Staff ATE Test Engineer, you will play a key role in the development, validation, and deployment of test solutions for advanced digital and mixed-signal SoCs. You'll collaborate closely with cross-functional teams-including design, product, and process engineering-to ensure robust test coverage, high yield, and smooth integration into high-volume manufacturing. Your expertise in ATE platforms, silicon debug, and data analysis will directly contribute to product quality, production efficiency, and time-to-market. This is a highly technical and impactful role suited for an engineer who thrives in a fast-paced, innovation-driven environment.

Collaborate with design and process engineering teams to develop and optimize test programs for digital and mixed-signal SoCs on Advantest 93K ATE platforms.
Ensure smooth integration of test programs into high-volume manufacturing environments.
Apply strong understanding of digital and analog fundamentals, Design-for-Test (DFT), and manufacturing concepts.
Support post-silicon validation, silicon bring-up, debugging, root cause analysis of circuit marginalities, and product/foundry interface.
Develop and debug test programs for digital and mixed-signal SoCs using VLSI ATE tools.
Utilize strong programming skills in C++ and Java, and scripting in Perl or Python for tool and test automation.
Work with test equipment including Advantest V93000 SoC Tester (Smartest 7 or 8), oscilloscopes, and logic analyzers.
Analyze production test data to monitor trends, identify yield issues, and drive test time reductions.
Provide timely technical support to manufacturing and subcontractor teams for test-related issues.
Lead root cause investigations of RMAs using electrical and physical failure analysis techniques.
Debug silicon, test boards, and ATE setups to address performance drifts, yield losses, or test escapes.
Collaborate cross-functionally to implement corrective actions and drive continuous improvement.
Document and clearly communicate technical findings to stakeholders.
Drive standardization and optimization of test methodologies to improve efficiency, quality, and cost-effectiveness.
Correlate lab bench and ATE test results to ensure measurement alignment.
Review device specifications and work with design teams to incorporate DFT strategies.
Support production ramp-up and sustaining activities through engagement with suppliers, foundries, and OSATs.

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in SoC test engineering, ideally in a high-volume manufacturing setting.
Hands-on experience with Advantest ATE platforms (e.g., 93K).
Strong expertise in silicon debug, failure analysis, and yield enhancement.
Excellent analytical, communication, and problem-solving skills.
Experience working with external vendors and cross-functional teams (e.g., OSATs, foundries).
Ability to work onsite at least 3 days per week in our Aliso Viejo, CA or San Jose, CA office.

Background in chip design (circuit/physical design or DV), including timing closure, power analysis, or block-level test development.
Experience with post-silicon physical debug (e.g., speed-path/Vmin analysis, memory arrays, clocking, yield improvements).
Proficiency in post-silicon logic debug, scan/memory dump analysis, and DFX feature utilization.
Understanding of embedded software, bootloaders, micro-kernels, and ability to modify system-level tests.
Knowledge of product engineering concepts, including ATE coverage, binning strategies, margin analysis, and scan pattern generation.
Familiarity with high-speed PHYs such as DDR, PCIe, MIPI, etc.

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