Staff Analog Design Engineer

Marvell•Santa Clara, CA

40d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. As an Analog Design Engineer with Marvell, you'll be a member of the Central Engineering business group. Central Engineering organization provides most advanced and key analog IPs to all businesses within Marvell: including Data Center, AI Networking, optical connectivity, Storage, Security. You'll be part of a key analog team that makes an outsized impact not only the organization but also to the technological arc of innovation in the field of High Speed SerDes Links. Our team is an experienced group of analog and mixed signal engineers that work on ADC based analog fronts and provide standalone IPs that cover multiple applications in support of all business units. We are currently focused on the development of cutting-edge ADC based SerDes IPs for high speed electrical and optical connectivity. As an analog circuit design engineer, you will be collaborating with system architects and a team of circuit and physical designers to build best in class serial links for various applications and space. Your work would swing between research and development geared towards circuits at bleeding edge of technology and data rates to hands-on ('roll-up-the sleeve') design of key analog circuits such as PLL, DLLs, ADCs, DACs CTLE/Filters, TX, RX, CDRs etc.

Requirements

MS/PhD 3+ years of direct analog design experience. Experience leading a complex block or project is highly preferred.
Expertise in one or more of the following focus areas of analog design: ADC/DACs, Front-Ends, CTLE, PLL, Timing circuits, CDRs, SerDes.
Ability to collaborate with various other design and functional teams: Layout/ Physical design, System architecture, Digital design and Validation for the successful development, release and support of complex mixed signal IPs
Keen eye for analog layout in latest deep submicron technologies and supervision of the same to get the key performance for high-speed design
Excellent debug skills to drive test plans and support validation for full cycle development of IPs and products