STA Engineer
ACL Digital•Santa Clara, CA
275d
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About The Position
The position requires a skilled engineer with a strong background in Electrical Engineering, specifically focusing on timing closure and static timing analysis (STA) for high-performance System on Chip (SoC) designs. The role involves collaboration with design and DFT teams to ensure effective implementation and validation of timing constraints, as well as running SOC timing analyses at various hierarchies. The engineer will also be responsible for analyzing timing results, facilitating necessary logic changes, and providing feedback to physical design engineers to achieve timing closure.
