Sr. Staff Physical Design PPA Engineer

Samsung Electronics America Inc•Austin, TX

33d

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Sr Staff Physical Design PPA Engineer. you will be responsible for developing and innovating design recipes aimed at improving Power/Performance/Area used for Physical Design execution on SARC/ACL premium IPs. The role requires a contributor with strong problem-solving skills, high-proficiency in all areas of Physical Design Implementation, and a comprehensive approach to delivering solutions.

Requirements

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
Solid understanding of the SOC/ASIC design flow with particular experience in taping out designs
Experience with synthesis, block, and full chip implementation utilizing the latest industry P&R/STA flows and tools
Experience in block level floor-planning, implementing power grid and area/congestion optimization
Proficient scripting/programming skills in TCL, Perl, Shell, and/or Python
Knowledge of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must

Nice To Haves

Experience with 7nm Finfet or smaller process nodes
Hands-on experience with clock tree synthesis (CTS)
Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure

Responsibilities

You will lead PPA initiatives by identifying opportunities, tracking progress, and executing towards delivering solutions that meet project requirements.
You will drive flows and methodologies improvements for the purpose of automating Physical Design Implementation, leveraging your strong problem-solving skills and high-proficiency in all areas of Physical Design. You will collaborate with stakeholders to ensure that your solutions meet their needs and expectations.
You will have hands-on responsibility from synthesis to place and route of an IP block through signoff flows, including timing and physical verification. You will work on synthesis, floor planning, place & route in chip-level and hierarchical physical implementation environments, ensuring that your designs meet PPA targets and signoff requirements.
You will interact with RTL counterparts and SOC teams to resolve design issues pertaining to block closure, providing feedback and working together to optimize the design flow. You will utilize your comprehensive approach to delivering solutions, ensuring that your work is of the highest quality and meets or exceeds expectations for frequency, power, and area requirements.