Sr. Staff Physical Design Manager

Marvell Technology•Westborough, MA

33d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering physical design organization at Marvell is a global team of highly-skilled engineers focused on designing next-generation chips for cloud data center and AI applications. As a manager within the PD team, you will have the opportunity to lead an experienced and growing team of physical design, static timing and design verification engineers. You will also have a technical role in the organization. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What You Can Expect Provide technical direction, coaching, and mentoring for a team of 4-6 employees to help them achieve breakthroughs in their careers Make decisions for talent management activities including hiring, reviewing, rewarding, retaining and developing employees Balance driving technical deliverables with managing team career development Assist in planning and allocating project resources, monitor progress, and keep stakeholders informed the entire way Partner with other ASIC and processor design teams to ensure project success When needed, act as management interface to external customers Hold a technical leadership role in the organization and be actively involved with project work suited to your background, interest and skills

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience
Minimum 3 years of experience as a people manager
Strong background in ASIC or SOC development
Recent, hands-on technical experience in physical design and/or STA from RTL handoff to GDS tape-out including skills such as floor planning, place and route, clock tree synthesis, timing closure and physical verification
Ability to handle a wide variety of projects and technical challenges.
Diligent, detail-oriented, and able to handle assignments with minimal supervision
Excellent written and oral communication skills, and ability to collaborate and be effective in fast-paced environment
Self-driven individual with ability to partner with world-wide team

Nice To Haves

Technical leadership of ASIC or SOC RTL to GDS tape-out
Experience as either top-level physical design lead, STA chip Lead or another SOC/ASIC leadership role
Experience with advanced technology nodes (7nm, 5nm and below)
Project management experience of ASIC or SOC
Experience working with team located in multiple geographies

Responsibilities

Provide technical direction, coaching, and mentoring for a team of 4-6 employees to help them achieve breakthroughs in their careers
Make decisions for talent management activities including hiring, reviewing, rewarding, retaining and developing employees
Balance driving technical deliverables with managing team career development
Assist in planning and allocating project resources, monitor progress, and keep stakeholders informed the entire way
Partner with other ASIC and processor design teams to ensure project success
When needed, act as management interface to external customers
Hold a technical leadership role in the organization and be actively involved with project work suited to your background, interest and skills